The present invention relates to a method of forming a semiconductor device, and more particularly to a method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions for a multiple-valued mask programmable read only memory in a reduced number of code selective ion-implantation processes.
In the mask programmable read only memory, ROM codes are decided in accordance with data supplied by the users. In order to decide the ROM code, it is necessary to carry out a plurality of code ion-implantation processes, wherein different mask patterns formed by photo-lithography processes are used to selectively ion-implant boron into selected cell transistor channel regions of the mask programmable read only memory. The selected, cell transistor channel regions having received boron implantation increase in threshold voltage level V.sub.T. The unselected cell transistor channel regions free of boron implantation remain unchanged in threshold voltage level V.sub.T. As a result of the plural code ion-implantation processes, the cell transistor channel regions have individually different threshold voltage levels. The difference in threshold voltage level of the cell transistor channel regions forms data. If two different threshold voltage levels are written into the cell transistor channel regions, this means that those cell transistor channel regions have binary digit data. If three or more different threshold voltage levels are written into the cell transistor channel regions, this means that those cell transistor channel regions have multiple valued data. In this case, the mask programmable read only memory is so called as a multiple-valued mask programmable read only memory.
FIG. 1 is a fragmentary plane view illustrative of arrays of cell transistor channel regions of a multiple-valued mask programmable read only memory.
The multiple-valued mask programmable read only memory has alternating alignments of a plurality of stripe-shaped n+-type buried regions 101 and 102 extending in a first horizontal direction and a plurality of rectangular-shaped p+-type isolation regions 200 which are aligned in the first horizontal direction so that each of the stripe-shaped p+-type isolation regions 200 isolates adjacent two of the stripe-shaped n+-type buried regions 101 and 102. Each pair of the stripe-shaped n+-type buried regions 101 and 102 sandwiches the alignment in the first horizontal direction of stripe-shaped p+-type isolation regions 200. The stripe-shaped n+-type buried regions 101 and 102 form source and drain regions of each cell transistor respectively. The stripe-shaped n+-type buried region 101 also serves as a ground line. The stripe-shaped n+-type buried region 102 also serves as a bit line.
The multiple-valued mask programmable read only memory further has a plurality of word lines 103 which extend in parallel to each other and in a second horizontal direction perpendicular to the first horizontal direction along which the stripe-shaped n+-type buried regions 101 and 102 extend. The word lines 103 extend cross over the stripe-shaped n+-type buried regions 101 and 102. The word lines 103 also serve as gate electrodes. First, second and third square-shaped cell transistor regions "a", "b" and "c" are represented by dotted lines. The rectangular-shaped p+-type isolation regions 200 isolates the first and second square-shaped cell transistor regions "a" and "b". Each of cell transistor channel regions 104 is positioned under the word line 103 and is sandwiched between the rectangular-shaped p+-type isolation regions 200 in the first horizontal direction and also sandwiched between the stripe-shaped n+-type buried regions 101 and 102. The threshold voltages of the cell transistor channel regions 104 are set to decide ROM-codes by boron-implantations carried out in accordance with the data supplied by the users.
FIGS. 2A through 2G are fragmentary cross sectional elevation views illustrative of a plurality of sequential ion-implantation processes involved in a conventional method of setting multiple threshold voltage levels of cell transistor channel regions of the multiple-valued mask programmable read only memory. Four different threshold voltage levels of the cell transistor channel regions of the multiple-valued programmable read only memory are set by combined uses of code ion-implantations into a p-well region over a silicon substrate. The four different threshold voltage levels, for example, first, second, third and fourth threshold voltage levels V.sub.T0, V.sub.T1, V.sub.T2, and V.sub.T3, are set by first, second and third code ion-implantations into the individual cell transistor channel regions of the four-valued programmable read only memory in accordance with data from the user. The first threshold voltage level V.sub.T0 is the lowest threshold voltage level. The second threshold voltage level V.sub.T1 is the second lowest threshold voltage level. The third threshold voltage level V.sub.T2 is the second highest threshold voltage level. The fourth threshold voltage level V.sub.T3 is the highest threshold voltage level.
With reference to FIG. 2A, a p-well region 300 is formed over a silicon substrate. Field oxide films are selectively formed on the p-well region 300 over the silicon substrate to define an active region surrounded by the field oxide films. A gate oxide film 301 is formed on the active region of the p-well region 300. Further, gate electrodes are formed on the surface of the gate oxide film 301 so that the gate electrode are aligned at a constant pitch, wherein only four gate electrodes, for example, first to fourth gate electrodes 302a, 302b, 302c and 302d are illustrated.
With reference to FIG. 2B, a photo-resist is applied on an entire surface of the silicon substrate for subsequent photo-lithography process to form a photo-resist pattern 303 over the filed oxide film so that the photo-resist pattern 303 has an opening positioned over the active region or the gate electrodes 302a, 302b, 302c and 302d.
With reference to FIG. 2C, an ion-implantation of boron into an upper region of the p-well region 300 is carried out by use of the photo-resist pattern 300 and the gate electrodes 3a, 3b, 3c and 3d as masks, whereby p-type isolation regions 304a, 304b, 304c, 304d and 304e are formed in the upper region of the p-well region 300 and positioned under apertures between the gate electrodes 302a, 302b, 302c and 302d. This ion-implantation of boron is carried out at an ion-implantation energy of 20 KeV, and at a dose of about 1.times.10.sup.13 cm.sup.-2. The formations of the p-type isolation regions 304a, 304b, 304c, 304d and 304e define first to fourth cell transistor channel regions 305a, 305b, 305c and 305d. The first cell transistor channel region 305a is defined between the first and second p-type isolation regions 304a and 304b and also is positioned under the first gate electrode 302a. The second cell transistor channel region 305b is defined between the second and third p-type isolation regions 304b and 304c and also is positioned under the second gate electrode 302b. The third cell transistor channel region 305c is defined between the third and fourth p-type isolation regions 304c and 304d and also is positioned under the third gate electrode 302c. The fourth cell transistor channel region 305d is defined between the fourth and fifth p-type isolation regions 304d and 304e and also is positioned under the fourth gate electrode 302d. The first, second, third and fourth cell transistor channel regions 305a, 305b, 305c and 305d have the first threshold voltage level V.sub.T0 as the lowest threshold voltage level.
With reference to FIG. 2D, the used photo-resist pattern 303 is removed before a photo-resist pattern 306 is provided over the substrate, wherein the photo-resist pattern 306 has two openings which are positioned over the second and fourth gate electrodes 302b and 302d. A first code ion-implantation of boron is carried out by use of the above photo-resist pattern 306 as a mask at an ion-implantation energy of 180 KeV and a dose in the range of about 1.0.times.10.sup.13 to about 2.0.times.10.sup.13, so that boron atoms penetrate through the gate oxide film 301 and the second to fourth gate electrodes 302b and 302d and are ion-implanted into the second to fourth cell transistor channel regions 305b and 305d under the second and fourth gate electrodes 302b and 302d. As a result of the first code ion-implantation of boron, the first threshold voltage level V.sub.T0 of the above second and fourth cell transistor channel regions 305b and 305d is risen to the second threshold voltage level V.sub.T1 as the second lowest threshold voltage level, whilst the first threshold voltage level V.sub.T0 of the above first and third cell transistor channel regions 305a and 305c remains unchanged.
With reference to FIG. 2E, the used photo-resist pattern 306 is removed before a photo-resist pattern 307 is formed over the silicon substrate. The photo-resist pattern 307 has two openings which are positioned over the third gate electrode 302c and the fourth gate electrode 302d respectively, so that the third and fourth gate electrodes 302c and 302d are shown through the two openings of the second photo-resist pattern 307, whilst the first and second gate electrodes 302a and 302b as well as the gate oxide film 301 and the field oxide film are covered by the photo-resist pattern 307. A second code ion-implantation of boron is carried out at an ion-implantation energy of 180 KeV and at a dose in the range of 3.0.times.10.sup.13 cm.sup.-2 to 4.0.times.10.sup.13 cm.sup.-2 by use of the photo-resist pattern 307 as a mask, so that boron atoms penetrate the third and fourth gate electrodes 302c and 302d and the gate oxide film 301 and are ion-implanted into the third and fourth cell transistor channel regions 305c and 305d positioned under the third and fourth gate electrodes 302c and 302d shown through the openings of the photo-resist pattern 307, whereby the third and fourth cell transistor channel regions 305c and 305d have the third threshold voltage level V.sub.T2 as the second highest threshold voltage level, whilst the first and second cell transistor channel regions 305a and 305b having the first and second threshold voltage levels V.sub.T0 and V.sub.T1 remain unchanged.
With reference to FIG. 2F, the used photo-resist pattern 307 is removed before a photo-resist pattern 308 is formed over the silicon substrate. The photo-resist pattern 308 has a single opening which is positioned over the fourth gate electrode 302d, so that the fourth gate electrode 302d is shown through the single opening of the photo-resist pattern 308, whilst the first, second and third gate electrodes 302a, 302b and 302c as well as the gate oxide film 301 and the field oxide film are covered by the photo-resist pattern 308. A third code ion-implantation of boron is carried out at an ion-implantation energy of 180 KeV and at a dose in the range of 1.0.times.10.sup.14 cm.sup.-2 to 2.0.times.10.sup.14 cm.sup.-2 by use of the photo-resist pattern 308 as a mask, so that boron atoms penetrate the fourth gate electrode 302d and the gate oxide film 301 and are ion-implanted into the fourth cell transistor channel region 305d positioned under the fourth gate electrode 302d shown through the single opening of the photo-resist pattern 308, whereby the fourth cell transistor channel region 305d having the third threshold voltage level V.sub.T2 as the second highest threshold voltage level rises in threshold voltage level to the fourth threshold voltage level V.sub.T3 as the highest threshold voltage level. In the meantime, the first, second and third cell transistor channel regions 305a, 305b and 305c having the first, second and third threshold voltage levels V.sub.T0, V.sub.T1 and V.sub.T2 remain unchanged. As a result of the third code ion-implantation, the first cell transistor channel region 305a has the first threshold voltage level V.sub.T0 as the lowest threshold voltage level. The second cell transistor channel region 305b has the second threshold voltage level V.sub.T1 as the second lowest threshold voltage level. The third cell transistor channel region 305c has the third threshold voltage level V.sub.T2 as the second highest threshold voltage level. The fourth cell transistor channel region 305d has the fourth threshold voltage level V.sub.T3 as the highest threshold voltage level.
With reference to FIG. 2G, the used photo-resist pattern 308 is removed. Implementation of the above combined three code ion-implantations, for example, the first, second and third code ion-implantation processes could set four different threshold voltage levels, for example, the first, second, third and fourth threshold voltage levels V.sub.T0, V.sub.1, V.sub.T2, and V.sub.T3 to the first, second, third and fourth cell transistor channel regions 305a, 305b, 305c and 305d, whereby the first cell transistor channel region 305a has the first threshold voltage level V.sub.T0 as the lowest threshold voltage level, the second cell transistor channel region 305b has the second threshold voltage level V.sub.T1 as the second lowest threshold voltage level, the third cell transistor channel region 305c has the third threshold voltage level V.sub.T2 as the second highest threshold voltage level, and the fourth cell transistor channel region 305d has the fourth threshold voltage level V.sub.T3 as the highest threshold voltage level.
As described above, it is necessary for the conventional method to implement at least the three code ion-implantation processes. The above conventional method is hard to reduce the number of the necessary code ion-implantation processes to set the four different threshold voltage levels, for example, the first, second, third and fourth threshold voltage levels V.sub.T0, V.sub.1, V.sub.T2, and V.sub.T3 to the first, second, third and fourth cell transistor channel regions 305a, 305b, 305c and 305d. The difficulty in reduction in the number of the necessary code ion-implantation processes results in a difficulty in shortening the turn around time.
Further, it is more serious problems that the first, second and third code ion-implantation processes are carried out by implanting boron which is light in weight. Boron impurity light in weight is likely to show any excess thermal diffusion by a heat treatment to be carried out in a later manufacturing process. This excess thermal diffusion results in substantive variations in threshold voltage level of the cell transistor channel regions 305a, 305b, 305c and 305d by the heat treatment.
In Japanese laid-open patent publication No. 6-318683, there is disclosed the following second, third and fourth conventional methods other than the above conventional method for setting the four different threshold voltage levels to the cell transistor channel regions of the four-valued programmable read only memory.
In the second conventional method, four mask patterns are used to carry out four ion-implantations of boron at different four dose levels D1, D2, D3 and D4 to set different four threshold voltage levels.
In the third conventional method, three mask patterns are used to carry out three ion-implantations of boron into a first threshold voltage level region at different three dose levels D2, D3 and D4 to set different four threshold voltage levels.
In the fourth conventional method, two mask patterns are used to carry out two ion-implantations of boron into a first threshold voltage level region at different two dose levels D1 and D2, wherein one of the cell transistor channel region is subjected to both the two ion-implantations, thereby to set different four threshold voltage levels.
The above second, third and fourth conventional methods are, however, engaged with the above serious problems with the excess thermal diffusion by a heat treatment to be carried out in a later manufacturing process. This excess thermal diffusion results in substantive variations in threshold voltage level of the cell transistor channel regions by the heat treatment.
Further, the above second and third conventional methods are also engaged with the problem with the difficulty in reduction in the number of the necessary code ion-implantation processes, resulting in a difficulty in shortening the turn around time.
In the above circumstances, it had been required to develop a novel method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions for a multiple-valued mask programmable read only memory, free from the above problems.